library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity auxiliar is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
selector : in std_LOGIC;
Liga : in std_logic_vector (3 downto 0);

DE: out std_logic_vector (3 downto 0));


end auxiliar;
architecture Behavioral of auxiliar is

constant s0 : std_logic_vector(3 downto 0) := B"0000";
begin
process (clk,reset,selector)
begin
if reset='1' then DE <=s0;
elsif rising_edge (clk) then
			if(selector='0')
				then resultado <= D;
			elsif (selector='1')
				then resultado <= Q;
			else resultado <= s0;	
			end if;
		end if;
end process;
end Behavioral;